University of Minnesota
University Relations
http://www.umn.edu/urelate
612-624-6868
myU OneStop


Go to unit's home.

Home | Seminars and Symposia | Past seminars/symposia: Wednesday, April 7, 2004

DTC Seminar Series

rePLay: A Hardware Framework for Dynamic Program Optimization

by

Sanjay J. Patel
Electrical and Computer Engineering
University of Illinois at Urbana-Champaign

Wednesday, April 7, 2004
1:00 pm

402 Walter Library

Sanjay J. Patel

Download slides (pdf 519 KB) Over the last several years, there has been a flurry of activity in the computer systems research community around the notion of dynamic optimization. Dynamic optimization offers the potential of optimizing code around short-term, phased program behavior. Dynamic information, such as branch behavior, memory dependence relationships, and cache effectiveness, is sampled and exploited by the dynamic optimizer to customize the code stream. In this manner, dynamic optimizers are able to optimize code in ways that would be difficult even for profile-driven static optimizers.

Sanjay J. Patel

The rePLay Framework is hardware framework for applying dynamic code optimization within high-performance processor pipeline. We have been investigating rePLay for the past four years, and derived techniques for region formation (frame construction), optimization (hardware optimizer), and region caching (frame cache). We have applied rePLay in the context of a simulated x86 processor where optimizations are performed at the micro-operation level. Because of the semantic gap introduced by the process of decoding complex x86 instructions into simple micro-operations, significant opportunity exists to "scrub" the micro-operation stream with a dynamic optimizer. In this talk we will describe our experiences with rePLay, present some of our major findings, present a blueprint of our hardware optimizer, and discuss some of our findings on the potential of dynamic optimization.

 

Sanjay J. Patel is an Assistant Professor of Electrical and Computer Engineering and Willett Faculty Scholar at the University of Illinois at Urbana-Champaign. He received his PhD from the University of Michigan, Ann Arbor in 1999. Patel is co-author (with Prof. Yale N. Patt at the University of Texas at Austin) of an introductory text book for computer science and engineering students, titled Introduction to Computing Systems: From bits and gates to C and beyond, which is now available in its second edition. His research interests include processor microarchitecture, computer architecture, and high performance and reliable computer systems. His research group investigates high-performance and error-tolerant processor architectures for the 7 to 10 year time horizon. He received a BS and an MS in Computer Engineering from the University of Michigan.