DTC Leading Edge Seminar Series
Wednesday, April 27, 2011
3:30 p.m. reception
4:00 p.m. seminar
401/402 Walter Library
Low power, high bandwidth main memory systems and storage will be a major architectural focus in the next three–five years. Chip stacking with through-silicon via's (TSV) opens a door of innovation not available to computer architects in the past 25 years. The presentation reviews key topics in future high performance DRAM systems and storage.
This presentation will also cover the architecture of Micron's high performance PCIe SSD controller. The history and design trade-offs in creating a one million IOP design, and various performance trade-offs from a platform perspective. What in today's computer architecture is pushing back against ultra-high performance storage?
Joe Jeddeloh is Director of Controller Development, DRAM Solutions, at Micron Technology. Mr. Jeddeloh has worked for Micron for the past 16 years. He has 175 patents in the areas of memory system architecture and controller development. His responsibilities include the management of the Micron Minneapolis Design Center. Prior to Micron, Mr. Jeddeloh designed cache and memory system at Unisys. Mr. Jeddeloh holds a Bachelor of Science degree in electrical engineering from the University of Minnesota.