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Home | Seminars and Symposia | Past seminars/symposia: Tuesday, October 18, 2005

DTC Science and Technology Innovators Lecture Series

High Performance Throughput Computing

by

Marc Tremblay
Sun Fellow and VP
Chief Architect, Scalable Systems Group

Tuesday, October 18, 2005
5:00 p.m. Reception
5:30 p.m. Seminar

402 Walter Library

THROUGHPUT COMPUTING, achieved through a new generation of microprocessors composed of multiple multi-threaded cores, can lead to performance improvements that are 10 to 30x those of conventional processors and systems. In this talk Marc Tremblay will discuss how the value of a robust, high-performance single thread leads to even higher throughput rates. He will also describe some of the techniques we are implementing in future mainstream processors that accomlish the somewhat conflicting goal of attacking both latency and throughput.

 

Dr. Marc Tremblay is a Sun Fellow, Vice President, and Chief Architect for Sun's Scalable Systems Group. In his role Tremblay sets future directions for Sun's processor and system roadmap. His mission is to move the entire product line to the Throughput Computing paradigm, incorporating techniques he has helped develop over the past several years, including; Chip Multiprocessing, Chip Multithreading, speculative multithreading, and assist threading. Tremblay holds a M.S. and Ph.D. in Computer Science from UCLA and a B.S. in Physics Engineering from Laval University in Canada. He holds 101 US patents in various areas of computer architecture. Tremblay was nominated for Innovator of the year by EDN Magazine in 1999. He was the Co-Chair of the Hot Chips 2000 Conference and most recently delivered the keynote address for The 31st Annual International Symposium on Computer Architecture (ISCA 2004) in Munich, Germany. He taught a graduate course on computer architecture at Stanford in 2002.Tremblay is a member of IEEE and ACM.