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Home | Seminars and Symposia | Past seminars/symposia: Thursday, October 18, 2007

DTC Seminar Series

Towards Statistical Design of Digital ICs

by

Michael Orshansky
Department of Electrical and Computer Engineering
The University of Texas at Austin

Thursday, October 18, 2007
10:00–11:00 am

402 Walter Library

The increasing variability of process parameters leads to substantial parametric yield losses due to timing and leakage power constraints. Leakage power is especially affected by variability because of its exponential dependence on the highly varying transistor channel length and threshold voltage. In this talk I address the problem of parametric yield analysis and optimization at several layers of the design and fabrication flow.

I first discuss our recent work in timing analysis under uncertainty. Statistical STA techniques assume that the full probabilistic distribution of timing uncertainty is available. In reality, the full probabilistic distribution information is often unavailable. I introduce a new paradigm for consistently and rigorously handling partially available descriptions of timing uncertainty using analytical operations with probabilistic interval variables. A provably correct strategy for fast Monte Carlo simulation based on probabilistic interval variables is also introduced.

I then talk about our work on enabling synthesis for parametric yield. We developed a new technology mapping algorithm that performs library binding to maximize parametric yield limited both by timing and power constraints. Experiments show that moving the concerns about variability into logic synthesis is justified. Leakage-limited parametric yield can also be improved during post-synthesis optimization. I present an efficient algorithm formulated as a rigorous statistical robust optimization program with a guarantee of power and timing yields. Power reduction is performed by simultaneous sizing and dual threshold voltage assignment. An extremely fast run-time is achieved by casting the problem as a second-order conic problem and solving it using efficient interior-point optimization methods. Post-silicon tuning is another valuable method for yield improvement. We demonstrate that co-optimization between two different paradigms for yield improvement — design-time optimization and post silicon tuning — is effective, and we present a formal framework based on adjustable optimization. Finally, I address the challenge of realizing circuits in fabrics that are characterized by extremely high defect densities. High defect densities are likely to occur in emerging nanotechnologies, such as those based on carbon nanotubes. I present techniques based on coding theory for implementing Boolean functions in highly defective fabrics that allow us to tolerate errors to a certain degree. The novelty of this work is that the structure of Boolean functions is exploited to minimize the redundancy overhead.

 

Michael Orshansky received the Ph.D. degree in electrical engineering and computer science from University of California, Berkeley, in 2001. He is currently an Assistant Professor of electrical and computer engineering at the University of Texas, Austin. Prior to that, he was a Research Scientist and Lecturer with the Department of Electrical Engineering and Computer Science at the University of California, Berkeley. His research interests include circuit design and analysis techniques for manufacturability of high-performance digital and mixed-signal circuits, statistical CAD algorithms for design-for-manufacturing and yield improvement, algorithms for low-power IC design, and modeling and simulation of semiconductor devices. He is the recipient of the National Science Foundation CAREER award for 2004. He received the 2004 IEEE Transactions on Semiconductor Manufacturing Best Paper Award, and the Best Paper Awards at the Design Automation Conference 2005, International Symposium on Quality Electronic Design (ISQED) 2006, and International Conference on Computer-Aided Design (ICCAD) 2006.