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Home | Seminars and Symposia | Past seminars/symposia: Tuesday, March 23, 2004

DTC Science and Technology Innovators Lecture Series

Towards Petaflops-scale Computing through Advanced PIM Architecture


Thomas Sterling
Center for Advanced Computing Research
California Institute of Technology

Tuesday, March 23, 2004
4:30 p.m. Reception
5:00 p.m. Seminar

402 Walter Library

Thomas Sterling

Fired by the realization of exponential growth as codified by the famous observation made by Gordon Moore, semiconductor technology has catalyzed an explosive gain in computational power that is unprecedented for any technology in the history of western civilization. As measured by the Linpack benchmark and represented by the "Top 500 List," delivered performance by the fastest machines in the world has almost doubled every year for the last decade. But behind this dramatic progression has been the equally important advances in parallel computer architecture that has exploited the underlying technology improvements. Even as the technology appears to progress steadily, the computer architectures that incorporate it and release its potential have gone through dramatic and fundamental changes that would constitute multiple revolutions in any other field. In spite of the apparent successes of current conventional MPP and commodity cluster architectures, low efficiencies and new performance opportunities are driving high end computer architecture towards yet another revolution in computer architecture, one that will establish the trajectory of future computers traversing the trans-Petaflops performance regime. These new architectures will exploit the opportunity to employ a hundred times as many processors as we use today and expose a 100X memory bandwidth in systems of equivalent scale. At the same time, they will reduce many of the factors that degrade performance efficiencies in today's conventional systems through innovative mechanisms for latency management, low overhead, and exploitation of fine grain parallelism. Among these are processor-in-memory (PIM) architectures that embed processing logic directly on the memory chips. A new generation of advanced PIM architecture is under development and being evaluated at Caltech and the University of Notre Dame that incorporates low-level strategies and support mechanisms for efficient data intensive near fine grain operation. Incorporated within these new PIM architectures is on-chip virtual to physical address translation, multithreaded parallel execution control, message driven computation through lightweight parcels, and simultaneous multiword operation directly on the contents of full memory rows. This address will present the concepts and evaluation of this new class of advanced PIM architecture and will consider its role both as a standalone component in "sea of PIM" system configurations and as a support component in a heterogeneous systems.

Sterling presenting
Reception photoReception photo


Thomas Sterling is a leader in the field of innovative high performance computer architecture. He received his Ph.D. from MIT as a Hertz fellow two decades ago, he has conducted extensive research in advanced parallel computer structures and computational models. He is a leader in the National Petaflops Initiative, a loose confederation of experts and institutions across the country sponsored by the federal government to investigate concepts and technologies for enabling systems capable of achieving performance in the trans-Petaflops regime. From 1996 to 2000 Dr. Sterling was the Principal Investigator of the HTMT project involving more than a dozen institutions and 70 contributors to conduct a design study of a potential future Petaflops scale computer incorporating advanced technologies including superconducting logic, optical communications, holographic storage, and processor in memory (PIM) components. Dr. Sterling and his team at Caltech and JPL are currently developing a new class of advanced PIM architecture for efficient scalable HEC and he is collaborating with a number of institutions on related research including the University of Notre Dame, Argonne National Laboratory, Sandia National Laboratory, the University of Delaware, and Cray.