University of Minnesota

Home | DTI | 2004–05 funded proposals | Jaijeet Roychowdhury, Wei-Chung Hsu

Initiatives in Digital Technology: 2004–05 Funded Proposals

Jaijeet Roychowdhury, Wei-Chung Hsu

Speeding up circuit simulation by optimizing cache/memory utilization

With semiconductor technologies continuously shrinking, circuit simulators are being called upon to verify larger and larger circuits, with concomitant increases in computation time. There is great interest in techniques to make such computation more efficient without incurring any loss of functionality. We propose a novel approach for delivering significant underlying speedups to all circuit simulation tasks: targetted, dynamic cache optimization of the MOSFET and other semiconductor devices that account for the majority of circuit-related computations. Combining concepts and approaches from the hitherto disparate areas of circuit simulation and dynamic cache optimization, our multi-disciplinary approach is expected have significant impact on the simulation of large circuits in industry. The PIs Roychowdhury and Hsu together bring to the project an ideal combination of appropriate expertise. The main purpose of this seed project is to obtain results based on which longer-term, externally-funded grants can be applied for. Preliminary results are presented that testify to the promise of our approach.

Contact Information

Digital Technology Center

499 Walter Library, 117 Pleasant Street SE, Minneapolis, MN 55455

P: (612) 624-9510

Connect on Social Media